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High speed dynamic buffer
閱讀：872發(fā)布：2023-06-17
專利匯可以提供High speed dynamic buffer專利檢索，專利查詢，專利分析的服務(wù)。并且Disclosed is a high speed insulated gate field effect transistor output buffer circuit integrated on a monolithic clip utilizing novel voltage drive circuitry. The circuit combines high speed with low operating voltages to provide a bipolar TTL compatible circuit.，下面是High speed dynamic buffer專利的具體信息內(nèi)容。
1. An insulated gate field effect transistor output buffer circuit integrated on a semiconductor chip comprising: a. first circuit means for receiving a logic input signal and operable to provide as an output the delayed complement of said logic input signal; b. second circuit means for receiving said logic input signal and operable to provide an output that consists of said input signals delayed by a predetermined interval; c. first and second IGFETs connected serially between circuit ground and a first voltage supply, respectively, having an output terminal at the common source-drain connection; d. third and fourth IGFET connected in series between a second voltage source and circuit ground, respectively, having the gate of said fourth IGFET commonly connected to the gate of said first IGFET, the common source and drain being connected to the gate of said second IGFET, and the gate of said third IGFET being coupled to the output of said first circuit means; and e. gating means coupling said delayed input signal to said common gates of said first and fourth IGFETs.
2. The output buffer circuit of claim 1 wherein said common source-drain connection of said third and fourth IGFET is coupled to a first clock signal by a capacitor.
3. The output buffer circuit of claim 2 wherein said gate of said third IGFET is coupled to a second clock signal by a capacitor.
4. The output buffer circuit of claim 3 wherein said first circuit means comprises an IGFET inverting delay circuit.
5. An output buffer circuit of claim 2 wherein said second circuit means comprises an IGFET non-inverting delay circuit.
6. The output buffer circuit of claim 3 wherein said gating means comprises an IGFET having its gate coupled to the output of said second circuit means by a capacitor.
7. The output buffer circuit of claim 6 wherein said first circuit means comprises: a. sixth and seventh IGFETs connected in series between said second power supply and circuit ground, respectively, having gate of said sixth IGFET for receiving said third clock signal and having the common source-drain connection as output terminal; and b. an eighth IGFET having its drain connected to said gate of said seventh IGFET, having its source connected to receive said data input signals, and having its gate for receiving said first clock signals, said source being coupled to said first clock by a capacitor.
8. The output buffer circuit of claim 7 wherein said second circuit means comprises: a. ninth and tenth IGFETs connected in series between said second voltage supply and said first clock signal, respectively, having the gate of said ninth IGFET connected to said first clock signal and having an output connection at the common source-drain connection; b. a capacitor connected between the gate of said tenth IGFET and said second clock signal; c. eleventh and twelfth IGFETs connected in series between said second voltage supply and circuit ground, respectively, the gate of said eleventh IGFET being connected to said first clock signal, and the common source-drain connection being connected to said gate of said tenth IGFET: d. a capacitor connected between the gate of said twelfth IGFET and said second clocking signal; and e. a thirteenth IGFET having its drain connected to said gate of said twelfth IGFET, having its source for receiving said input signal, and having its gate connected to said first clock signal.
9. An insulated gate field effect transistor output buffer circuit integrated on a semiconductor chip comprising: a. first circuit means for receiving a logic input signal and operable to provide as an output the delayed complement of said logic input signal b. second circuit means for receiving said output of first circuit means and operable to provide an output that consists of said input signals delayed by a predetermined interval; c. first and second IGFETs connected serially between circuit ground and a first voltage supply, respectively, having an output terminal at the common source-drain connection; d. third and fourth IGFETs connected in series between a second voltage source and circuit ground, respectively, having the gate of said fourth IGFET commonly connected to the gate of said first IGFET, the common source and drain being connected to the gate of said second IGFET, and the gate of said third IGFET being coupled to the output of said first circuit means; and e. gating means coupling said delayed input signal to said common gates of said first and fourth IGFETs.
10. The output buffer circuit of claim 9 wherein said common source-drain connection of said third and fourth IGFET is coupled to a first clock signal by a capacitor.
11. The output buffer circuit of claim 10 wherein said gate of said third IGFET is coupled to a second clock signal by a capacitor.
12. The output buffer circuit of claim 11 wherein said first circuit means comprises an IGFET inverting delay circuit.
13. The output buffer circuit of claim 12 wherein said second circuit means comprises an IGFET non-inverting delay circuit.
14. The output buffer circuit of claim 13 wherein said gating means comprises an IGFET having its gate coupled to the output of said second circuit means by a capacitor.
15. The output buffer circuit of claim 11 wherein said first circuit means comprises: a. sixth and seventh IGFETs connected in series between said second power supply and circuit ground, respectively, having gate of said sixth IGFET for receiving said third clock signal and having the common source-drain connection as output terminal; and b. an eighth IGFET having its drain connected to said gate of said seventh IGFET, having its source conNected to receive said data input signals, and having its gate for receiving said first clock signals, said source being coupled to said first clock by a capacitor.
16. The output buffer circuit of claim 15 wherein said second circuit means comprises ninth and tenth IGFETs connected in series between said second voltage supply and said first clock signal, respectively, having the gate of said ninth IGFET connected to said first clock signal, having the gate of said tenth IGFET connected to said output of said first circuit means, and having the common source-drain connection as an output terminal.
17. The output buffer circuit of claim 4 wherein said predetermined interval of said second circuit means is one-half bit longer than the delay of said first circuit means.
18. The output buffer circuit of claim 9 wherein said predetermined interval of said second circuit means is one-half bit longer than the delay of said first circuit means.
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